One of the most significant of these new concepts is advanced packaging, which essentially accommodates an ever-increasing number of transistors by decreasing the size of electrical contacts. Traditionally, a semiconductor chip focuses on performing one particular action or process. By comparison, an advanced multichip package incorporates multiple chips and processes into one component. This transformative approach integrates a multitude of semiconductor components into a single package, directly addressing the most critical semiconductor technical and commercial constraints. (See Exhibit 1.)

Advanced multichip packaging improves performance and time to market while reducing chip manufacturing costs and power consumption. Moreover, because it is such a radical change in chip integration, unlocking greater functionality and a reduced form factor, advanced packaging of chips is perfectly suited for key applications such as mobile devices and, in the coming years, automotive computing and generative artificial intelligence (GenAI).

For chipmakers, investors, and computing device and equipment makers, the emergence of advanced packaging represents a radical shift in the semiconductor industry landscape. The next generation of industry-leading organizations will be those that realize value creation is migrating towards companies that can design and integrate complex, system-level chip solutions using concepts like advanced packaging. Merely making individual components will rapidly lose luster, replaced by collaborative efforts that bring together the best in design, packaging, and system integration to meet the demands of the market.

Package or Perish

We are now in the “More than Moore” era. As predicted by Gordon Moore himself, it was inevitable that his law would eventually meet a threshold of diminishing economic returns. As the industry reaches the physical limitations of transistor density and chip size, the costs to cram more into a small space are exploding. But rather than try to squeeze additional transistors onto a single chip, advanced multichip packaging enables the combining of smaller, cost- and performance-optimized dies—the unpackaged semiconductor chips comprised of functional integrated circuits. It does so by using high-bandwidth interconnects and the latest front-end or wafer fabrication technologies to unleash the combined power of the packaged components. Perhaps most importantly, each of these components can have a different purpose, with computing and memory running on smaller technology nodes than components that have already reached their scaling limits, such as input/output blocks.

These components can be placed in closer proximity on advanced substrates, driving data transfer rates up to 35 times faster than the latest motherboard. This also allows for the reuse of die designs across multiple systems because the modular components can be combined in any number of ways to drive various and varied applications. By contrast, more widely used systems on a chip (SoC) are only designed for a single application.

Four examples illustrate the advantages of advanced packaging. (See Exhibit 2.) The NVIDIA Hopper H200 is one of the most innovative AI core graphics processing units (GPUs) today. Six high-bandwidth memory (HBM) stacks are packaged with the central IC chips, allowing for interconnection speeds of up to 4.8 TB/s. Conventional systems, where chips are connected via a printed circuit board, are typically limited to less than 200 GB/s. Close interconnect distances also drastically decrease the power consumption of these chips, making the data centers that power large language models (LLMs) economically feasible.

The second example is the AMD Ryzen series. By opting for multiple smaller chips rather than a single large SoC, designers were able to select from a range of node sizes for each of the heterogeneously integrated dies and choose chips that were optimized for each of the package’s functions. This approach cut manufacturing costs by as much as 50%. The smaller die sizes contribute to this cost reduction by increasing fabrication yield rates because the same number of defects on a wafer is distributed across more dies.

The third illustration involves chip area size. By integrating the individual chips used in Optireg linear voltage controllers into an advanced package, Infineon was able to reduce the part’s footprint by 60%. Condensing the space required for complex systems enables a new generation of compact devices without compromising computational power or functionality. This miniaturization is key in industries where space is at a premium, such as in mobile and Internet of Things (IoT) devices, small medical equipment like hearing aids and pacemakers, and automotive computing systems.

Finally, Intel, among other integrated design manufacturers (IDMs), has greatly expanded investment in the manufacturing sides of its business to develop advanced multichip packaging capabilities. Intel has already shown that switching from a single large SoC to multiple dies in its Data Center GPU Max Series can minimize die complexity and allow existing die designs to be reused in multiple packages. In the process, Intel found that this can reduce time to market by up to 75%.

Advanced Packaging Shakes Up the Value Chain

Advanced packaging accounts for about 8% of the total semiconductor market today and is projected to double by 2030 to more than $96 billion, outpacing the rest of the chip industry. Currently, consumer electronics like smartphones dominate advanced packaging applications, but the burst of activity in the AI segment will propel future growth. AI requires rapid data exchange between computing and memory elements, which is enabled by 2.5D and 3D packaging. These approaches place more than two chips next to each other to generate high interconnect speeds at a relatively low cost. AI applications account for 25% of the total advanced packaging market already, and this is poised to grow at around 20% per year through the next decade.

As this growth trend picks up speed, advanced packaging will change the semiconductor ecosystem significantly. (See Exhibit 3.) Traditionally, the value chain of chipmaking was rather simple: one chip designer, one front-end manufacturer, and a back-end company for packaging and testing. Sometimes all these roles are handled by the same integrated device manufacturer. In this scenario, the lion’s share of value capture is concentrated in chip design and the front end—where most of the innovation lies—while packaging is relegated to a lower-margin role.

• Elevating the Role of System Design. The value share contributed by advanced package design will rise significantly, underscoring its strategic importance. (See Exhibit 4.) In response, chip designers are solidifying their grasp on this crucial segment by extending design from the single chip to the whole system, including integrating multiple dies into an advanced package.
• Shifting from Front End to Back End. The package will become a point of innovation, a differentiation driver pivotal to system performance. While front-end manufacturing will continue to command a high share of value generation, back-end design and packaging will gain in importance and profit value.
• Adapting to Complexity. Making advanced semiconductor packages is a complex process. To manage it, electronic design automation (EDA) software must be programmed to design and simulate multiple chips in a package and how their interplay may impact operating conditions, such as thermal dissipation and warpage. Similarly, materials suppliers must develop new, innovative materials to address, among other things, thermal expansion and heat transfer at the numerous interfaces in advanced packages. And packaging equipment must be modified to meet the decreasing feature sizes and increasing precision requirements of advanced packaging.

The Altered Face of the Chip Industry

As these technology changes take hold, the face of the semiconductor industry will be altered in significant ways. Chiefly, there will be a much greater degree of collaboration across chip design, package engineering, and system architecture, as each will directly impact the other. One die’s power profile will affect the next die’s thermal load and may require customized materials to optimize system performance.

Like today’s front-end landscape in which chip design and manufacturing co-evolve, strategic partnerships will increasingly extend from multiple front-end players to back-end package manufacturing. A good example of this, NVIDIA’s Hopper H100, uses a TSMC CoWoS-S package, which combines chips designed by NVIDIA and manufactured by TSMC with HBM designed and manufactured by SK Hynix. Another illustration: chip designers today work with a specific foundry’s fabrication process development kit in their electronic design automation software when building a chip. Tomorrow, this kit may contain the specific package solution in a similar manner.

Another potential area of greater collaboration will involve GenAI and machine intelligence. Integrated in EDA software, artificial intelligence capabilities can automate IC layout and floor planning; optimize power, performance, area (PPA), the essential component of semiconductor design; and simplify and expedite chip production to an unparalleled degree. But as the success of AI platforms is strongly dependent on the size and accuracy of its learning dataset, EDA software vendors and chip designers will have to balance pooling internal blueprints and frameworks to enhance the AI knowledge base without revealing their design secrets to competitors.

And even as companies jockey for position, geopolitical and regulatory constraints and opportunities will arise to affect supply chains and market access. Subsidies for advanced multichip packaging are increasingly in vogue as governments try to attract, retain, and support technology innovation in chipmaking. At the same time, since semiconductors are considered critical for national and economic security, trade barriers are being erected in various regions to protect domestic manufacturing. However, these measures could impact the availability of supplies, partners, and customers for semiconductor companies.

Strategic Solutions for Semiconductor Players

With so much change in the offing due to advanced packaging, different players in the semiconductor industry will need to adopt distinct strategic imperatives to position themselves for sustained differentiation and value capture. Here’s a breakdown of how segments of the industry can position themselves best. (See Exhibit 5.)